Design and Optimization of A 4-bit Absolute-value Detector Using Half Adder and Comparator

Abstract In this paper, a design and optimization of 4-bit absolute value detector is realized by using the CMOS technique, transmission gates, traditional comparator, which can compare two positive input values all expressed in binary form. To optimize overall performance detector, paper chooses to minimize number transistors simplifies circuit through logical analysis. As for calculating delay energy consumption, critical path identification also studied analyzed paper. Based on theory effort parasitic delay, grid capacitance resistance are introduced into calculation inverter ratios. achieve various objectives, study combines size power supply voltage scaling techniques reduce circuit, finally finds minimum loss at 1.5x delay. The be multiple unit that. compromise, 1.5 times selected consumption 39.16 %.